The present invention relates to an input/output buffer, an input buffer, and an output buffer.
Due to the recent progress in multimedia and the popularity of asymmetric digital subscriber line (ADSL) and wireless LAN, the number of households having personal computers (PC) has increased. It is required that the power consumption be reduced in peripheral equipment of a personal computer. Thus, the circuits of the peripheral equipment are miniaturized and operated with low voltage. Such low voltage circuits must be protected when the circuits are not supplied with power or when the low voltage circuits are provided with a voltage signal that is greater than the operational voltage.
A PC is normally connected to a display, a mouse, a printer, a memory, a modem, or a game device by means of a bus or an input/output port (I/O port).
A bus is classified as an internal bus or an external bus. The internal bus connects the CPU and the memory. The external bus connects the CPU and an I/O port (e.g., graphic board or SCSI board). Examples of an external bus include, for example, industrial standard architecture (ISA), peripheral component interconnect (PCI), small computer system interface (SCSI), IEEE 1394, universal serial bus (USB), integrated drive electronics (IDE), and AT attachment (ATA).
The I/O port is an interface connecting the PC and the peripheral equipment and normally includes a port exclusive connector. The I/O port includes a serial port connected to, for example, a mouse and modem, a parallel port connected to a printer, and a game port connected to a game device.
FIG. 1 is an explanatory diagram illustrating a layout example of connection pins in a game port (joystick port), which is connected to a joystick. A joystick port connector 71, which includes +5 V (volts) power supply terminals, digital input terminals, analog input terminal, and ground terminals, may be connected to joysticks A and B. An example in which the joysticks A and B each have two buttons will now be discussed.
The +5 power terminals are normally directly connected to a motherboard, and current flows through the +5 power supply terminals to the motherboard. Digital signals (A1, A2, A3, A4 in FIG. 1) are input from the buttons of the joysticks A and B, which are connected to the port. The digital input terminals receive, for example, a signal having a low level (V) when the buttons of the joysticks A and B are pushed and a signal having a high level when the buttons of the joysticks A and B are not pushed.
The analog input terminals receive an analog signal (AX, AY, BX, BY) that is in accordance with the resistances of the joysticks A and B.
More specifically, the joystick port includes a one shot multivibrator 72 as shown in FIG. 2, which is connected to an analog input terminal via an input/output buffer 73. A resistor 74 having a resistance of, for example, 2.2 kΩ is connected between the analog input terminals and the multivibrator 72. A 0.011 μF timing capacitor 75 is connected between the output terminal of the multivibrator 72 and a ground terminal. The joysticks A and B each have a variable resistor 76 (0 to 100 kΩ). The resistor 76 has a first terminal connected to a +5 power supply terminal and a second terminal connected to the analog input terminal.
When the analog input terminal is provided with an analog signal from the joysticks A and B, the multivibrator 72 generates an output signal having a high level (5 V). The high output signal charges the capacitor 75. When the voltage of the capacitor 75 reaches 3.3 V, the multivibrator 72 generates a signal at a low level (0 V). When the multivibrator 72 is outputting the high signal, the resistance of the joysticks A and B is proportional to the resistance of the variable resistors 76. In other words, position information of the joysticks A and B may be detected from the resistance of the variable resistor 76.
Due to the decrease in the operational voltage of the interface (I/O port), the circuits used in peripheral equipment are not operated under the same power supply voltage. Thus, an input/output buffer for the I/O port must be able to accept signals having a voltage that is greater than the operational voltage of the input/output buffer.
For example, when the power supply voltage of the input/output buffer 73 is 3.3 V, a 5 V voltage signal for operating the joysticks A and B is input to the input terminal of the input/output buffer 73. In this case, the input/output buffer 73 must be able to accept a 5 V voltage signal.
The following input/output buffers are known to be able to accept signals having a voltage that is greater than the power supply voltage:
first prior art example, input/output buffer having a tolerant function; and
second prior art example, input/output buffer having a voltage resistance function at a circuit section to which a voltage signal, which is greater than the operational voltage, is applied in the input/output buffer.
FIG. 3 is a schematic block diagram of an input/output buffer 81 according to the first prior art example. The input/output buffer 81 includes an input/output circuit 82, an input circuit 83, an output circuit 84, and a tolerant circuit 85.
The input/output circuit 82 sends a voltage signal EB, which is an external input signal, to the input circuit 83 and the tolerant circuit 85. The tolerant circuit 85 generates a voltage signal BP having a voltage that is in accordance with the input voltage signal EB. The input circuit 83 generates a signal X by adjusting the voltage signal EB (external input signal) to an optimal signal X and outputting the signal X to an internal circuit (not shown).
The output circuit 84 receives a data signal A and an output control signal C from the internal circuit. The output circuit 84 generates control signals AP and AN in accordance with an output control signal C and provides the control signals AP and AN to the input/output circuit 82. The input/output circuit 82 generates the voltage signal EB in response to the control signals AP and AN and sends the voltage signal EB to the external equipment.
The circuits of the input/output buffer 81 will be described in more detail. The output circuit is a generally used circuit and thus will not be discussed.
FIG. 4 is a circuit diagram of the input/output circuit 82. The input/output circuit 82 includes p-channel MOS transistors (PMOS transistors) Pt1 and Pt2 and n-channel MOS transistors (NMOS transistors) Nt1 and Nt2.
The transistors Pt1 and Pt2 are connected in series, and the source of the transistor Pt1 is connected to a first high voltage power supply VDE. The gate of the transistor Pt1 receives the control signal AP from the output circuit 84. The drain of the transistor Pt1 is connected to the source of the transistor Pt2. The gate of the transistor Pt2 is connected to a low voltage power supply VSS, and the drain of the transistor Pt2 is connected to the drain of the transistor Nt1.
The back gates of the transistor Pt1 and the transistor Pt2 are each connected to the output of the tolerant circuit 85 and has substantially the same voltage as the voltage signal BP, which is generated by the tolerant circuit 85.
The transistors Nt1 and Nt2 are connected in series, and the source of the transistor Nt2 is connected to the low voltage power supply VSS. The drains of the transistors PT2, Nt1 are connected to each other, and a node N1 between the transistors Pt2 and Nt1 is connected to an input/output terminal 82a of the voltage signal EB. A first high voltage power supply VDE is a power supply for supplying an external circuit that is connected to the input/output buffer 81 with operational voltage and has, for example, a voltage of 3.3 V. The low voltage power supply VSS is the ground (GND).
The gate of the transistor Nt1 is connected to the first high voltage power supply VDE, and the back gate of the transistor Nt1 is connected to the low voltage power supply VSS. The gate of the transistor Bt2 receives the control signal AN from the output circuit 84, and the back gate of the transistor Nt2 is connected to the low voltage power supply VSS.
FIG. 5 is a circuit diagram of the tolerant circuit 85. The tolerant circuit 85 includes a resistor R1 and PMOS transistors Pt3 to Pt5.
The resistor R1, which is an input protection circuit, has one end connected to the node N1 (input/output circuit 82) of the input/output circuit 82 and another end connected to the gate of the transistor Pt3. The resistor R1 decreases the voltage of the voltage signal EB, which is input to the input/output circuit as an external input signal). The voltage signal EB of which voltage has been decreased (voltage signal EBR) is provided to the gate of the transistor Pt3.
The source of the transistor Pt3 is connected to the first high voltage power supply VDE, and the drain of the transistor Pt3 is connected to the source of the transistor Pt4. The transistors Pt4 and Pt5 are connected in series and have gates that are connected to the first high voltage power supply VDE. The drain of the transistor Pt5 is connected to a node N2 between the resistor R1 and the transistor Pt3. The drain of the transistor Pt5 is provided with the gate voltage of the transistor Pt3 (voltage signal EBR).
The back gates of the transistors Pt3 to Pt5 are connected to the back gates of the other transistors and to a node between the transistors Pt3 and Pt4. The tolerant circuit 85 outputs the voltage signal BP, the voltage of which is the same as the voltage at the node between the transistors Pt3 and Pt4.
FIG. 6 is a circuit diagram of the input circuit 83. The input circuit 83 includes PMOS transistors Pt6 to Pt8 and NMOS transistors Nt3 to Nt7. The drain of the transistor Nt3 is connected to the first high voltage power supply VDE, and the source and gate of the transistor Nt3 are connected to each other. The transistors Nt4 and Nt5 are connected in series, and the gates of the transistors Nt4 and Nt5 are connected to the first high voltage power supply VDE. The source of the transistor Nt5 is connected to the node N2 of the tolerant circuit 85 and receives the gate voltage of the transistor Pt3 (voltage signal EBR). The drain of the transistor Nt4 is connected to the source of the transistor Nt3, and the voltage at node N3 between the transistors Nt4 and Nt3 is supplied to the gates of the transistors Pt7 and Nt6. The back gates of the transistors Nt3 to Nt5 are each connected to the low voltage power supply VSS.
The source of the transistor Pt6 is connected to the first high voltage power supply VDE, and the gate of the transistor Pt6 is connected to the node N2 of the tolerant circuit 85 to receive the voltage signal EBR. The drain of the transistor Pt6 is connected to the source of the transistor Pt7, and the transistor Pt7 is connected to the transistor Nt6. The source of the transistor Nt6 is connected to the low voltage power supply VSS. The back gates of the transistors Pt6 and Pt7 are connected to the output of the tolerant circuit 85 and have about the same voltage as the voltage signal BP. The back gate of the transistor Nt6 is connected to the low voltage power supply VSS.
The gates of the transistors Pt8 and Nt7 are connected to the drains of the transistors Pt7 and Nt6. The source of the transistor Pt8 is connected to a second high voltage power supply VDI, and the drain of the transistor Pt8 is connected to the drain of the transistor Nt7. The source of the transistor Nt7 is connected to the low voltage power supply VSS. The second high voltage power supply VDI is a power supply for supplying the internal circuit with operational voltage and has, for example, 1.8V. The back gate of the transistor Pt8 is connected to the second high voltage power supply VDI, and the back gate of the transistor Nt7 is connected to the low voltage power supply VSS. The signal X, which has the drain voltage of the transistors Pt8 and Nt7, is provided to the internal circuit (not shown).
An example in which the voltage signal EB (external input signal) is input to the input/output buffer 81 will now be discussed.
1. Case in which the voltage signal EB is close to the voltage of the low voltage power supply VSS:
In this case, the transistor Pt3 switches on in the tolerant circuit 85. Accordingly, the tolerant circuit 85 outputs the voltage signal BP, the voltage of which is the same as the first high voltage power supply VDE.
In the input circuit 83, the transistor Pt6 switches on and the source of the transistor Pt7 is connected to the first high voltage power supply VDE. In this state, the power supply VDE activates the transistors Nt4 and Nt5, and the transistor Nt3 is inactivated. This inputs the voltage signal EBR to the gates of the transistors, which in turn, activates the transistor Pt7 and inactivates the transistor Nt6. As a result, the gates of the transistors Pt8 and Nt7 are connected to the high voltage power supply VDE. This inactivates the transistor Pt8 and activates the transistor Nt7. Accordingly, the input circuit outputs the signal X, which has the voltage of the low voltage power supply VSS, that is, a low level.
2. Case in which the voltage signal EB is close to the voltage of the high voltage power supply VDE (under the condition that EB<VDE is satisfied):
In this case, in the tolerant circuit 85, it is difficult for the transistors Pt3 to Pt5 to switch on, and the transistors Pt3 to Pt5 substantially function as a series-connected resistor. Accordingly, the tolerant circuit 85 outputs the voltage signal EBR, or the voltage signal BP that has about the same voltage as the first high voltage power supply VDE.
In the input circuit 83, the transistor Pt6 switches off. In this state, although it is difficult for the transistors Nt3 to Nt5 to switch on since the gate-source voltage is small, a voltage signal having a voltage that is slightly lower than that of the high voltage power supply VED (e.g., the voltage signal being about 3.1 V when the high voltage power supply VDE has 3.3 V) is input to the gates of the transistors Pt7 and Nt6. In response to the voltage signal, the transistor Pt7 switches on and the transistor Nt6 switches on. As a result, the low voltage power supply VSS is connected to the gates of the transistors Pt8 and Nt7. This activates the transistor Pt8 and inactivates the transistor Nt7. Accordingly, the input circuit 83 outputs the voltage of the second high voltage power supply VDI, or the signal X at a high level.
3. Case in which the voltage signal EB exceeds the first high voltage power supply VDE:
In this case, in the tolerant circuit 85, the transistor Pt5 switches on since its source voltage (voltage signal EBR) is greater than the gate voltage (high voltage power supply VDE). In this state, the transistor Pt4 switches on in the same manner. Accordingly, the tolerant circuit 85 outputs the voltage signal BP, the voltage of which is about the same as that of the voltage signal EB.
In the input circuit 83, the transistor Pt6 is inactivated. In this state, the transistor Nt4 switches off since its source voltage (voltage signal EBR) is greater than the gate voltage (high voltage power supply VDE). In the same manner, the transistor Nt5 switches off. However, the gate voltage of the transistor Nt3 increases and activates the transistor Nt3. In this state, the gates of the transistors Pt7 and Nt6 are provided with the voltage signal, the voltage of which is decreased from that of the first high voltage power supply VDE by the threshold voltage of the transistor Nt3. In response to the voltage signal, the transistor Pt7 switches off, and the transistor Nt6 switches on. As a result, the gates of the transistors Pt8 and Nt7 are connected to the low voltage power supply VSS. This activates the transistor Pt8 and inactivates the transistor Nt7. Accordingly, the input circuit 83 outputs the voltage of the second high voltage power supply VDI, or the signal X at a high level.
The back gates of the transistors Pt6 and Pt7 have the same voltage as that of the voltage signal (voltage adjusted in accordance with the voltage signal EB). Thus, even if the voltage of the voltage signal EB is greater than that of the first high voltage power supply VDE, the gate voltage becomes greater than the back gate voltage and prevents the generation of a leak current in the transistors Pt6 and Pt7. Accordingly, the input/output buffer 81 adjusts the voltage signal EB to a proper voltage (the operational voltage of the internal circuit) and outputs the voltage signal EB even if an external input signal having the voltage signal EB (e.g., 5 V), which is greater than the operational voltage (3.3 V), is input to the input/output buffer 81.
When the first high voltage power supply VDE does not supply the input/output buffer 81 with power (inactivated state), devices may be damaged and a leakage current may flow in the input/output buffer 81. Normally, in a personal computer or the like, a power supply circuit is continuously supplied with power. In this state, a voltage signal may be input to the inactivated input/output buffer 81 from an external circuit. In such a case, the application of a voltage greater than the power supply voltage may damage devices or produce leakage current.
More specifically, if the high voltage signal EB is input to the input/output buffer from an external device when the input/output buffer 81 is not supplied with power (high voltage power supply VDE), voltage greater than that of the power supply VDE is applied between the gate and drain of the transistor Pt2 and the gate and source of the transistors Nt1, Pt3, Pt5, Pt6, and Nt5. In such a case, high voltage, which is greater than the operational voltage, is applied to the gate oxidization film of each transistor. This produces short circuits between gates and drains and between gates and sources. Thus, the input/output buffer 81 is not suitable for equipment having a hot plug function.
In the input/output buffer having a voltage resistance function at the predetermined circuit sections, the gate oxidation film that directly receives the high voltage signal must be formed thickly while the gate oxidization films of the other transistors are formed with the normal thickness. This increases the circuit cost and increases the processing time.
To solve the above problem, Japanese Laid-Open Patent Publication No. 2000-29551 uses a buffer protection circuit, which will now be discussed.
FIG. 7 is a circuit diagram of a prior art voltage generator 91, which is a buffer protection circuit. The voltage generator 91 includes PMOS transistors 92 to 94 and NMOS transistors 95 to 97. The source of the transistor 92 and the gate of the transistor 95 are connected to a power supply VDD. The drain of the transistor 95 is connected to the gate of the transistor 92, and the source of the transistor 95 is connected to a power supply VSS (ground). Two diode-connected transistors 96 and 97 are connected in series between the drain of the transistor 92 and a terminal PAD.
When the power supply voltage VDD exists, the voltage generator 91 generates the reference voltage VDD2 having about the same voltage as the power supply voltage VDD. When the power supply voltage VDD does not exist, the voltage generator 91 drops the voltage of the voltage signal input to the terminal PAD by a voltage corresponding to two diodes. The voltage generator 91 adjusts the voltage signal input to the terminal PAD to a proper voltage and generates reference voltage VDD2. This protects circuits from high voltage signals input to the terminal PAD regardless of whether or not the power supply VDD exists.
However, the voltage generator 91 (FIG. 7) has the shortcomings described below.
(1) The back gates of the transistors are connected to the power supply VSS (ground). Thus, when the power supply VDD does not exist (VDD=0), high voltage is applied between the gate and back gate of each of the transistors 96 and 97. This causes device deterioration. Such a shortcoming also occurs when the transistors 96 and 97 are PMOS transistors.
(2) To sufficiently control the voltage drop in the diode-connected transistors 96 and 97, the transistor 94 configures a DC path between the terminal and the power supply VSS. However, in the DC path, the voltage of the power supply VDD decreases to about the same voltage as the power supply VSS. Further, when the transistor 94 is activated, the reference voltage VDD2 decreases. Thus, the reference voltage VDD2 having the intended voltage level cannot be generated. When an NMOS transistor configures the transistor 94 and the power supply VSS configures the gate input of the transistor 94, the path through which current flows is eliminated. As a result, the high voltage signal input to the terminal PAD cannot be decreased to the proper voltage to generate the reference voltage VDD2.
(3) The forward direction of the diode configured by the transistors 96 and 97 is the direction from node A to the terminal PAD. Thus, when the voltage at node A becomes greater than that at the terminal PAD (e.g., if the voltage of the voltage signal provided to the terminal PAD is the same as the voltage of the power supply voltage (ground)), current flows from the node A to the terminal PAD. This decreases the reference voltage VDD2 and the reference voltage VDD2 cannot be generated with the intended voltage level. If a high voltage signal is input to the terminal PAD when PMOS transistors configure the transistors 96 and 97, the effect of junction temperature increases the resistance of each PMOS transistor. This increases the difference between the voltages applied to each PMOS transistor and damages the device.